The current state of the art comprises of the arrangement of R, G and B display subpixels to form a single display pixel. A typical configuration for a low resolution display is highlighted in FIG. 1, where discrete R, G and B ILED chips are packed together to provide the necessary light for each pixel of the display. In this example, each R, G and B chip has one emitter per chip. The typical/minimum size of these R, G, B chips is 50 μm×50 μm. For larger displays with moderate resolution the one to one relationship between ILED chips and display sub pixel results in the requirement for a very large number of ILED chips. This raises significant manufacturability and cost challenges. For ultra-high resolution displays the size of the ILED chips limits the area and size of the pixel display and thus the overall display resolution. In this instance, the display pixel size is limited to 100 μm×100 μm area which is not sufficient to achieve a high resolution display sub 20 μm×20 μm in area.
An alternative approach may be to reduce the size of ILED chips. It is technically complicated and challenging to manufacture and place chips that are smaller than 20×20 μm on a substrate or driver backplane, which therefore limits the display pixel size (albeit at a low level). In addition this does not address the issue of the number of placement steps required. This would therefore remain technically and financially challenging.